ULPI - Kcchao
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
Standalone USB Transceiver Chip - EEWeb
USB 3.0 PHY for SoC Designs | Cadence IP
usb3300-ezk hi speed usb host or device phy with ulpi low pin interface
USB 2.0/HSIC PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
TUSB1210 data sheet, product information and support | TI.com
USB-IF certified solutions for USB type-C and Power Delivery - STMicroelectronics
XR2280x Hi-Speed USB to 10/100 Ethernet Bridge ICs - MaxLinear | Mouser
HSIC USB 2.0 PHY IP
Mixed-Signal Verification for USB 2.0 Physical Layer IP
Chip controls up to seven USB-C ports, and Power Delivery
USB 2.0 Device Controller IP Core (USB20SF)
USB 2.0 PHY for SoC Designs | Cadence IP
c++ - stm32 timing ULPI interface - Stack Overflow
USB 2.0 Solutions | Arasan Chip Systems
USB 2.0 PHY IP core | Arasan Chip Systems
Physical layer - Wikipedia
USB 2.0 extender control chipCH317 - NanjingQinhengMicroelectronics
USB3250 | Microchip Technology
